VPR：一种新的包装，布局和布线工具的FPGA研究

VPR：一种新的包装，布局和布线工具的FPGA研究(中文5200字,英文4100字)
摘 要
我们描述了一个基于FPGA新的功能和CAD工具使用的算法，各种途径和方（VPR）。在减少路由面积计算方面，VPR优于所有的FPGA布局布线工具，我们可以比较。虽然常用的算法是基于已知的方法，是我们目前而言改善运行时间和质量的几个有效方法。我们目前的版图和路由上的大型电路的一套新的结果，让未来的基准电路尺寸上的设计方法更多，用于今天的典型的FPGA布局布线工具工业品外观设计。VPR是针对一个范围广泛的FPGA架构的能力，并且源代码是公开的。它和相关的网表翻译/群集工具VPACK已经被用在世界各地的一些研究项目，并且是有用的FPGA体系结构的研究。
VPR: A New Packing， Placement and Routing Tool for
FPGA Research
Department of Electrical and Computer Engineering， University of Toronto
Toronto， ON， Canada M5S 3G4 {vaughn， jayar}@eecg.toronto.edu
Abstract
We describe the capabilities of and algorithms used in a new FPGA CAD tool，Versatile Place and Route (VPR). In terms of minimizing routing area， VPR outperforms all published FPGA place and route tools to which we can compare.Although the algorithms used are based on previously known approaches， we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today’s industrial designs.VPR is capable of targeting a broad range of FPGA architectures， and the source code is publicly available. It and the associated netlist translation /clustering tool VPACK have already been used in a number of research projects worldwide， and should be useful in many areas of FPGA architecture research.