基于FPGA的交通灯系统设计(附程序清单)

基于FPGA的交通灯系统设计(附程序清单)(论文13000字)
摘要：本次设计是以FPGA为基础来实现的道路交通灯控制与显示系统，该系统能够实现对信号灯的控制与显示功能与对时间的正常倒计时与显示功能，给道路上的行人以及车辆起到提示性的作用。它主要有三种工作状态：第一种为正常工作状态，红、绿、黄三种交通信号灯按设定循环工作；第二种为特殊状态，所有路口均显示为红灯并且提供蜂鸣报警；第三种工作状态为拥堵状态，通过增加压力传感器模块，来检测当前道路交通是否堵塞，并相应地去调整红绿灯所设定的时间。主要芯片运用了Altera公司所生产的Cyclone IV系列的EP4CE6E22C8N芯片，编程语言选择的是Verilog HDL语言，开发环境与仿真采用的是Quartus II 13.0。设计这个系统时，根据系统功能的要求，运用了模块化设计作为设计的思路，自顶而下地通过对系统各个模块的分类和设计，合理规划分配与设计并调试硬件电路模块，最后进行关于显示波形的仿真，显示了一个功能完整的道路交通信号灯控制系统。
关键词： 交通灯， FPGA ，QuartusII，Verilog HDL
 
The design of Traffic Light System Based on FPGA
Abstract：This design is based on the FPGA to achieve the realization of the road traffic light control and display system, the system can achieve the signal control and display function and the time of the normal countdown and display function, to the pedestrians on the road and the vehicle prompts The role of sex. It has three main working states: the first for the normal working state, red, green and yellow traffic lights according to set the cycle of work; the second for a special state, all the intersection are shown as red and provide a buzz alarm; The third working condition is the congested state, by increasing the pressure sensor module to detect whether the current road traffic is blocked, and accordingly to adjust the traffic lights set by the time. The main chip using the Altera Corporation produced CycloneIV series EP4CE6E22C8N chip, the programming language is selected Verilog HDL language, development environment and simulation using the QuartusII 13.0. Design of this system, according to the requirements of the system function, the use of modular design as a design idea,using from-top-to-down through the system of the various modules of the classification and design, reasonable planning and distribution and design and debugging hardware circuit module, and finally on the display The waveform of the simulation shows a complete function of the road traffic signal control system.
Key words：traffic lights；FPGA；QuartusII；Verilog HDL
 

目 录
1. 绪论
1.1研究背景及意义    1
1.2 国内外现状    1
1.3 研究内容    2
2. 设计要求与方案    2
2.1设计要求    3
2.2设计方案的选择    4
3. 硬件设计    5
3.1FPGA相关知识    5
3.1.1开发与设计    5
3.1.2工作原理    6
3.2具体硬件设计    7
3.2.1电源和时钟模块    8
3.2.2 按键与LED模块    9
3.2.3数码管模块    9
3.2.4蜂鸣器模块    10
3.2.5压力传感模块    10
4. 软件设计    13
4.1开发环境QuartusⅡ    13
4.2硬件描述语言Verilog HDL    14
4.3主要模块的设计与仿真    14
4.3.1顶层模块与控制模块的设计    14
4.3.2分频模块的设计    15
4.3.3计数模块的设计    16
4.3.4状态机模块的设计    17
4.3.5 LED显示模块的设计    18
4.3.6数码管显示与闪烁模块的设计    18
4.3.7蜂鸣器模块的设计    19
4.3.8压力传感器模块的设计    19
5.仿真结果与分析    20
5.1硬件实物结果    20
5.2软件仿真结果    21
5.3结果分析    21
6.总结    22
参考文献    23
致谢    24
附录    25